CASH: A C to Layout Compiler

In this paper we present CASH, a Compiler for Application Specific Hardware. CASH performs high-level synthesis, taking as input ANSI C programs, generating structural Verilog as output. The goal of this paper is to describe the research contributions incorporated in CASH, which advance the techniques of high-level synthesis in several directions. From the outset we set the goal for CASH to support ANSI C programs in their original form, enabling software programmers to create hardware devices. Another goal for CASH is to be able to exploit the parallelism available in the C programs. The granularity of parallelism extracted by CASH is instruction-level parallelism (ILP). Techniques for extracting ILP have been a subject of intense research and implementation in the last 40 years in the compiler domain. ILP is effectively leveraged by the modern superscalar and VLIWmicroprocessors. CASH incorporates many techniques from traditional software compilers and uses them to increase the parallelism of the synthesized circuits. Some of these techniques have been used before in the context of high-level synthesis, but CASH combines them together in novel ways. The following are important research contributions present in CASH: